1/6 data briefing december 2001 complete data available on data-on-disc cd-rom or at www.st.com complete data available on data-on-disc cd-rom or at www.st.com m7020r 32k x 68-bit entry network search engine features summary n 32k data entries in 68-bit mode n table may be partitioned into up to four (4) quadrants (data entry width in each octant is configurable as 34, 68, 136, or 272 bits.) n up to 83 million sustained searches per second in 68-bit and 136-bit configurations n up to 41.5 million searches per second in 34-bit and 272-bit configurations n searches any sub-field in a single cycle n offers bit-by-bit and global masking n synchronous, pipelined operation n up to 31 search engines cascadable without performance degradation n when cascaded, the database entries can scale from 248k to 1984k depending on the width of the entry n glueless interface to industry- standard srams n simple hardware instruction interface n ieee 1149.1 test acc ess port n operating supply voltages include: v dd (operating supply voltage) = 1.8v v ddq (operating supply voltage for i/o) = 2.5 or 3.3v n 272 pbga, 27mm x 27mm figure 1. 272-ball pbga package 272-ball pbga 27mm x 27mm
m7020r 2/6 description overview st microelectronics, inc.s m7020r search en- gine incorporates patent-pending associative pro- cessing technology? (apt) and is designed to be a high-performance, pipelined, synchronous, 32k-entry network database search engine. the m7020r database entry size can be 68 bits, 136 bits, or 272 bits. in the 68-bit entry mode, the size of the database is 32k entries. in the 136-bit mode, the size of the database is 16k entries, and in the 272-bit mode, the size of the database is 8k entries. the m7020r is configurable to support multiple databases with different entry sizes. the 34-bit entry table can be implemented using the global mask registers (gmrs) building-database size of 64k entries with a single device. performance the search engine can sustain 83 million transac- tions per second when the database is pro- grammed or configured as 68 or 136 bits. when the database is programmed to have an entry size of 34 or 272 bits, the search engine will perform at 41.5 million transactions per second. stms m7020r can be used to accelerate network proto- cols such as longest-prefix match (cidr), arp, mpls, and other layer 2, 3, and 4 protocols. applications this high-speed, high-capacity search engine can be deployed in a variety of networking and com- munications applications. the performance and features of the m7020r make it attractive in appli- cations such as enterprise lan switches and rout- ers and broadband switching and/or routing equipment supporting multiple data rates at ocC 48 and beyond. the search engine is designed to be scalable in order to support network database sizes to 1984k entries specifically for environ- ments that require large network policy databases. figure 4, page 5 shows the block diagram for the m7020r device. table 1. product range figure 2. switch/router implementation using the m7020r part number operating supply voltage operating i/o voltage speed temperature range m7020r-083za1 1.8v 2.5 or 3.3v 83mhz commercial m7020r-066za1 1.8v 2.5 or 3.3v 66mhz commercial M7020R-050ZA1 1.8v 2.5 or 3.3v 50mhz commercial program memory switch fabric switch processor network line interfaces system bus host asic sram bank search engine ai04272
3/6 m7020r table 2. signal names note: 1. signal types are: i = input only; i/o = input or output; o = output; and t = tristate 2. clk is an internal clock signal. any reference to clk cycles means one cycle of clk. 3. ack and eot signals require a weak, external pull-down resistor of 47 k w or 100 k w . symbol type (1) description clocks and reset clk2x i master clock phs_l i phase test i test input rst_l i reset command and dq bus cmd[8:0] i command bus cmdv i command valid dq[67:0] i/o address/data bus ack (4) t read acknowledge eot (4) t end of transfer ssf t search successful flag ssv t search successful flag valid sram interface sadr[21:0] t sram address ce_l t sram chip enable we_l t sram write enable oe_l t sram output enable ale_l t address latch enable cascade interface lhi[6:0] i local hit in lho[1:0] o local hit out bhi[2:0] i block hit in bho[2:0] o block hit out fuli[6:0] i full in fulo[1:0] o full out full o full flag device identification id[4:0] i device identification supplies v dd n/a chip core supply (1.8v) v ddq n/a chip i/o supply (2.5 or 3.3v) test access port tdi i test access ports test data in tck i test access ports test clock tdo t test access ports test data out tms i test access ports test mode select trst_l i test access ports reset
m7020r 4/6 figure 3. connections sadr 8 sadr 13 sadr 11 sadr 14 sadr 17 sadr 20 sadr 10 sadr 19 sadr 18 sadr 21 sadr 15 sadr 5 sadr 6 sadr 7 sadr 9 sadr 12 sadr 16 sadr 2 sadr 1 sadr 3 sadr 0 sadr 4 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc full eot nc nc nc nc ack nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc lhi6 lhi5 lhi4 lhi1 lho0 lho1 bhi0 bho0 bho1 bho2 fuli0 fuli3 fulo0 fulo1 fuli2 fuli1 fuli4 fuli5 fuli6 bhi2 bhi1 lhi0 lhi2 lhi3 nc nc nc nc nc nc nc nc nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd cmd8 cmd7 cmd5 cmd4 cmd3 cmd1 cmd6 cmd2 cmd0 cmdv dq17 dq15 dq13 dq11 dq9 dq1 dq5 dq7 dq21 dq27 dq31 dq33 dq29 dq25 dq23 dq19 dq35 dq37 dq43 dq53 dq57 dq61 dq63 dq67 dq59 dq55 dq49 dq64 dq62 dq60 dq66 dq58 dq56 dq50 dq48 dq46 dq44 dq42 dq38 dq30 dq36 dq32 dq34 dq28 dq20 dq24 dq22 dq16 dq18 dq8 dq0 dq2 dq4 dq12 dq10 dq14 dq6 dq26 dq40 dq52 dq54 dq51 dq45 dq41 dq39 dq47 dq65 dq3 tdo tms tck tdi id0 id2 id3 id1 id4 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd clk2x we_l oe_l ae_l ce_l phs_l ssf ssv rstl gnd t rst_l right bottom left top ai04270
5/6 m7020r figure 4. m7020r block diagram ai04271 comparand registers[15:0] global mask registers [7:0] information and command register burst read register burst write register next free address register search successful index registers [7:0] (all registers are 68-bit-wide) ta p controller pipeline and sram control arbitration logic command decode and pio access compare/pio data phs_l clk2x rst_l dq [67:0] cmd [8:0] cmdv ack eot cmd compare/pio data address decode priority encode match logic configurable as 64k x 34 32k x 68 16k x 136 8k x 272 data array configurable as 64k x 34 32k x 68 16k x 136 8k x 272 mask array full logic full [6:0] full fulo [1:0] id [4:0] lhi [6:0] bhi [2:0] ssf ssv lho [1:0] bho [2:0] ta p sadr [21:0] oe_l we_l ce_l ale_l
m7020r 6/6 part numbering table 3. ordering information scheme note: 1. where z is the symbol for bga packages and a denotes 1.27mm ball pitch for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m70 20 r C083 za 1 t device type m70 search engine density 20 = 2mb (32k x 68-bit table entries) operating supply voltage r = v dd = 1.8v speed C083 = 83 million searches per second C066 = 66 million searches per second C050 = 50 million searches per second package pbga = 272-ball count, 27mm x 27mm (1) , 1.27mm ball pitch temperature range 1 = 0 to 70c shipping optio n tape & reel packing = t
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